1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to structures for analyzing electromigration, and methods of using same.
2. Description of the Related Art
By way of background, modern integrated circuit devices, e.g., microprocessors, ASICs, memory devices, etc., are comprised of millions of field effect transistors formed on a semiconducting substrate, such as silicon. The substrate may be doped with either N-type or P-type dopant materials. An illustrative field effect transistor 10, as shown in FIG. 1, may have a doped polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g. arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown). Additionally, although not depicted in FIG. 1, a typical integrated circuit product is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
The gate electrode 14 has a critical dimension 12, i.e., the width of the gate electrode 14, that approximately corresponds to the channel length 13 of the device when the transistor 10 is operational. Of course, the critical dimension 12 of the gate electrode 14 is but one example of a feature that must be formed very accurately in modern semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc.
As device dimensions have continued to shrink, the packing density of the semiconductor devices, e.g., transistors, has increased. That is, ever increasing numbers of transistors or memory cells are located on the same plot space of a semiconducting substrate. As a result of this increased device density, the conductive metal lines and contacts or vias that connect these various devices have also been reduced in physical size, and they are also packed more closely together. In general, the resistance of a metal line is inversely proportional to the cross-sectional area of the metal line. Thus, all other things being equal, it is important that the cross-sectional area of the metal line be maintained above certain minimum levels such that the resistance of the metal line does not exceed allowable limits. Unanticipated increases in the resistance of a metal line may adversely impact device performance, e.g., a reduction in operating frequency, increased heat build-up, increased power consumption, etc.
Unfortunately, a phenomenon known as electromigration can adversely impact conductive metal lines in an integrated circuit product. In general, electromigration is a process whereby a conductive structure, such as a metal line, contact or via tends to degrade, thereby resulting in a change in the physical characteristics, e.g., shape, size, etc., of the conductive structure. Typically, electromigration occurs when a current is passed through relatively long conductive structures. The current sets up an electrical field in the conductive structure that decreases from the input side to the output side of the conductive structure. Additionally, heat generated by the flowing current sets up a thermal gradient along the conductive structure. As a result, the metal atoms in the conductive structure become mobile and diffuse within the conductive structure. This electromigration phenomenon results in physical changes to the size and/or shape of the conductive structure. For example, in some cases, the conductive structure may be thinned at one or more locations. In a worst case scenario, electromigration can cause complete separation of the conductive structure. This electromigration phenomenon can occur on metals such as aluminum, copper, tungsten, titanium, etc.
In designing integrated circuit products, efforts are taken to reduce, eliminate or account for electromigration of conductive structures in integrated circuit products. Such efforts may include selecting appropriate materials, making conductive structures sufficiently large such that the effects of electromigration does not adversely impact the performance of the integrated circuit product over its useful life.
Typically, one or more tests are performed on an integrated circuit product to determine its ability to withstand electromigration during the product lifetime. FIG. 2 is an illustrative test structure 30 that can be used for such purposes. The test structure 30 is comprised of a conductive metal line 32, a plurality of dummy metal lines 34, and contacts 36 coupled to each end of the conductive metal line 32. The lines 32, 34 have a layer of insulating material 38 positioned therebetween. A relatively high current, much higher than that anticipated in normal usage of the integrated circuit product, is passed through the conductive metal line 32 until such time as the resistance of the conductive metal line 32 increases by a preselected amount, e.g., 10% or 20%. The increase in resistance is due to material loss and/or change in shape of the conductive metal line 32 due to electromigration. The acceptability of the product as to its ability to withstand electromigration depends upon the time it takes for the conductive metal line to exhibit the established standard for increase in resistance. Such testing can be very time-consuming. For example, such an electromigration test may involve subjecting the conductive metal line 32 to the test current for 10-12 hours.
However, in forming the conductive metal line 32, the critical dimension 32A, i.e., width, of the conductive metal line 32 may vary from that anticipated by the design process. For example, the target critical dimension 32A of the conductive metal line 32 may be 180 nm. Due to variations and/or process bias in one or more of the process tools used in creating the metal line 32, e.g., a stepper exposure tool, an etch tool, etc., the actual critical dimension 32A may vary from that of the target value. For example, the manufactured conductive metal line 32 may have a critical dimension 32A that is actually 171 nm or 189 nm as compared to the target value of 180 nm. Thus, after the electromigration test is performed to breakdown, e.g., 20% increase in resistance, the conductive metal line 32 is typically cross-sectioned, and the critical dimension 32A is measured using a scanning electron microscope. Based upon the measured critical dimension, the duration to breakdown for a conductive metal line 32 having the target critical dimension 32A, e.g., 180 nm, is determined by extrapolating the electromigration data for the tested conductive metal line 32 having the measured critical dimension 32A.
Such a process can be very time-consuming in that it requires the cross-section of one or more portions of the wafer. Moreover, the feedback from the electromigration testing may not be available as quickly as would otherwise be desired.
The present invention is directed to various structures and methods that may solve, or at least reduce, some or all of the aforementioned problems.